1. Field of the Invention
The present invention relates to automatic layout of one or more elements of an integrated circuit, especially analog elements, and, more particularly, to the creation of conformal outlines used in the layout of these elements.
2. Brief Description of the Prior Art
In order to realize the high levels of integration that are occurring with system-on-chip designs, analog and digital functionality are being included on more semiconductor chips than ever. As more of these mixed signal chips are created, automation for the layout of the analog segments of these chips is required. Currently, this is an almost completely manual process.
An analog cell is typically a circuit, such as an operational amplifier or comparator, that includes between ten and one hundred elements, such as transistors, resistors and capacitors. In order to automatically lay out these elements to create a circuit, a large amount of detailed geometry needs to be optimized. For example, the placement of elements needs to take maximal advantage of design rules to create a compact and correct layout. One aspect of detailed geometric creation that can have a dramatic impact on the compactness and correctness of an analog cell layout is the well and latchup of protection geometry.
In a typical silicon semiconductor process, mask layers are created where each N-well is created and where each P-well is created. All N-type transistors must be surrounded by a P-type well and vice versa. These wells need to be electrically connected to the correct voltages or the transistors may not perform optimally, and in the worst case will not work at all. The geometry used to electrically connect the well to the rest of the circuitry is referred to as latchup protection geometry.
While the problems of creating wells and latchup protection geometry also occur in the layout of digital circuits, the solutions used to create well and latchup protection geometry for digital layouts are different than the solutions required for layout of analog cells. Specifically, for most digital cells, the transistors are very similarly sized and small. These transistors tend to share active regions in addition to sharing well geometry. The methodology most often used to create digital cells is to first define the areas of the cell where the P and N wells are positioned and then to place the transistors in those areas. In contrast, in an analog layout, the devices may be much larger and may also have differing sizes. Therefore, it is preferred to first place the devices, then form the wells around the devices.
Another difference between digital cell layout and analog cell layout is the voltage to which each well is connected. For digital layouts, the wells are almost always tied to power and ground. In contrast, analog circuits tend to have more wells that are tied to voltages other than power and ground.
In general, the rules on how a well geometry is created simply specify that the well geometry must enclose certain geometry of the devices by given amounts. The rules for where latchup protection must be formed in a well geometry, however, are more complicated. Specifically, latchup protection must be formed in the well area with the devices and must be placed so that it can effectively keep the entire well at a desired voltage. In general, this latter condition is expressed as a radius from which all the devices in the well must be located from the latchup protection geometry.
In addition to these physical rules, there are constraints on the performance of an automated solution for the creation of well and latchup protection geometry. Namely, it must be fast enough to be used in automatic layout where a large number of candidate solutions, each having well and latchup protection geometry, may need to be evaluated. The solution must also be fast enough to be used in an interactive mode to assist the designer with manual placement.
The wells that are created must also satisfy aesthetic constraints in order to be acceptable to designers. These constraints can be roughly expressed to be that the well shapes should have low complexity. Shapes with rough, jagged edges are generally not acceptable to designers. Moreover, designers prefer each well group to be as large as possible. However, this latter preference is in tension with the goal of any automated well layout system to minimize the well area utilized to receive the desired circuits.
It is, therefore, an object of the present invention to overcome the above problems and others by providing an automated method for creating well geometries for circuits, especially analog circuits. It is also an object of the present invention to minimize the area of the generated well geometry while, at the same time, avoiding overlap between the generated well geometry and one or more areas of an integrated circuit design where it is desired to avoid placing circuits or elements of a circuit. Still other objects will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.
Accordingly, we have invented a method of creating a conformal outline for layout of one or more devices on an integrated circuit. The method includes defining a plurality of input rectangles in a Cartesian coordinate system having a first axis and second axis, with each input rectangle having two edges parallel to the first axis and two sides parallel to the second axis. Coordinates on the first axis where the sides of each input rectangle sides reside are acquired and a sorted list is formed from the acquired coordinates. A variable I is initialized with the value of two (2) and first and second candidate rectangles having one of their respective sides positioned at the smallest and largest coordinates in the sorted list, respectively, are identified from the input rectangles. The other of the sides of the respective first and second candidate rectangles are set equal to the coordinate on the first axis stored in the Ith position in the sorted list, thereby forming a shared side. For each candidate rectangle having coordinates on the first axis which overlap coordinates of one or more input rectangles on the first axis, the lengths of the sides of the candidate rectangles are modified as necessary so that they extend from the maximum to the minimum second axis coordinates of the one or more input rectangles. If the shared side with respect to one candidate rectangle does not coincide with or overlap the shared side with respect to the other candidate rectangle, the length of the shared side with respect to the one candidate rectangle is modified as necessary so that it coincides with or overlaps the shared side with respect to the other candidate rectangle.
The method can also include the step of initializing a Best Solution variable that includes a cost.
The method can further include the steps of determining a cost of the candidate rectangles and, when the cost of the candidate rectangles is more advantageous then the cost of the Best Solution, updating the Best Solution with the position of the candidate rectangles in the Cartesian coordinate system and the cost determined therefor.
Next, the variable I is incremented by one (1) and a determination is made if I equals the number of coordinates in the sorted list. If not, the shared side is stepped or moved to the coordinate on the first axis stored in the Ith position in the sorted list. For each candidate rectangle having coordinates on the first axis which overlap coordinates of one or more input rectangles on the first axis, the lengths of the sides of the candidate rectangle are modified as necessary so they extend from the maximum to the minimum second axis coordinates of the one or more input rectangles. If the shared side with respect to one candidate rectangle does not coincide with or overlap the shared side with respect to the other candidate rectangle, the length of the shared side with respect to one rectangle is modified as necessary so that it coincides with or overlaps the shared side with respect to the other candidate rectangle. Next, the cost of the candidate rectangles is determined and the Best Solution is updated with the position of the candidate rectangles and the cost therefor when the cost is more advantageous than the current cost of the Best Solution. The foregoing steps are repeated until the value of the variable I equals the number of coordinates in the sorted list.
The cost of the candidate rectangles can be determined in numerous manners. One manner of determining the cost includes defining one or more penalty rectangles in the Cartesian coordinate system and determining an area of intersection between the candidate rectangles and the one or more penalty rectangles. The cost of the candidate rectangles can be determined based on at least two of (i) the area of the candidate rectangles; (ii) the area of intersection; and (iii) a penalty weight (PW) for the intersection.
Preferably, the cost is determined utilizing the following equation:   Cost  =            (              Area        ⁢                  xe2x80x83                ⁢        of        ⁢                  xe2x80x83                ⁢        Candidate        ⁢                  xe2x80x83                ⁢        Rectangles            )        +                  ∑                  k          =          0                          k          =          A                    ⁢              xe2x80x83            ⁢                        PW          k                *                              ∑                          i              =              0                                      i              =              B                                ⁢                      xe2x80x83                    ⁢                      Area            ⁢                          xe2x80x83                        ⁢            of            ⁢                          xe2x80x83                        ⁢            Intersection            ⁢                          xe2x80x83                        ⁢                                          (                                                      Penalty                    ⁢                                          xe2x80x83                                        ⁢                                          Rects                      k                                                        ,                                      xe2x80x83                                    ⁢                                      Candidate                    ⁢                                          xe2x80x83                                        ⁢                                          Rects                      i                                                                      )                            .                                          
where A=(No. of Penalty Rects. xe2x88x921); and
B=(No. of Candidate Rects. xe2x88x921).
We have also invented a method of creating a conformal outline for layout of one or more devices on an integrated circuit that includes defining a plurality of input rectangles in a Cartesian coordinate system having a first axis and a second axis, where each input rectangle has two edges parallel to the first axis and two sides parallel to the second axis. Coordinates on the first axis are acquired where the sides of each input rectangle reside and a sorted list is formed from the acquired coordinates. A variable I is initialized to two (2). Next, first and second candidate rectangles having one of their respective sides positioned at the smallest and largest coordinates in the sorted list, respectively, are identified from the input rectangles and a third candidate rectangle having its sides positioned between the smallest and largest coordinates in the sorted list is also identified from the input rectangles. The side of the first candidate rectangle opposite the smallest coordinate in the sorted list and one side of the third candidate rectangle are set equal to the coordinate on the first axis stored in the Ith position in the sorted list thereby forming a shared side. A variable J is initialized to the value of the variable I plus one (1), i.e., J=I+1. Next, the side of the second rectangle opposite the largest coordinate in the sorted list and the other side of the third candidate rectangle are set equal to the coordinate on the first axis stored in the Jth position in the sorted list, thereby forming another shared side. For each candidate rectangle having coordinates on the first axis which overlap coordinates of one or more input rectangles on the first axis, the lengths of sides of the candidate rectangle are modified as necessary so they extend from the maximum to the minimum second axis coordinates of the one or more input rectangles. When the shared side with respect to one candidate rectangle does not coincide with or overlap the same shared side with respect to the other candidate rectangle, the length of the shared side with respect to the one candidate rectangle is modified as necessary so that it coincides with or overlaps the same shared side with respect to the other candidate rectangle.
The method can also include determining a cost of the candidate rectangles and, when the thus determined cost is more advantageous than a cost of a Best Solution variable, the Best Solution variable is updated with the coordinates of the candidate rectangles in the Cartesian coordinate system and the cost determined therefor.
The foregoing steps, after initialization of the variable J, are repeated until the value of J equals the number of coordinates in the sorted list. When the value of J equals the number of coordinates in the sorted list, the value of I is incremented by 1 and the foregoing steps, after identifying the first, second and third candidate rectangles from the input rectangles, are repeated until the value of I equals the number of coordinates in the sorted list minus one (1).
We have also invented a method of creating a conformal outline for layout of one or more devices on an integrated circuit that includes the steps of defining a plurality of input geometries in a coordinate system having a first axis and a second axis where each input geometry has first and second edges parallel to the first axis and first and second sides parallel to the second axis. Coordinates on the first axis are acquired where the sides of each input geometry reside. A sorted list is formed from these acquired coordinates. A first candidate geometry is identified having its first side residing at the smallest coordinate in the sorted list and a second candidate geometry is identified having its second side residing at the largest coordinate in the sorted list. The second side of the first candidate geometry and the first side of the second candidate geometry are positioned at a coordinate in the sorted list between the smallest and largest coordinates thereby forming a shared side.
For each candidate geometry which has first axis coordinates which overlap first axis coordinates of one or more input geometries, and which has at least one second axis coordinate extreme which does not coincide with a second axis coordinate extreme of the one or more input geometries, the lengths of the sides of the candidate geometry are modified so that opposite ends of each side terminate at the respective second axis coordinate extremes of the one or more input geometries. When the shared side with respect to one candidate geometry does not coincide with or completely overlap the shared side with respect to the other candidate geometry, the length of the shared side with respect to the one candidate geometry is modified so that it coincides with or completely overlaps the shared side with respect to the other candidate geometry.
The method can also include determining for the combination first and second candidate geometries a cost therefor. If the thus determined cost is more advantageous than a previously determined cost or no cost, the thus determined cost is stored along with the position of the first and second candidate geometries relative to the input geometries. The foregoing steps, after forming the shared side at a coordinate in the sorted list between the smallest and largest coordinates, are repeated for each position of the shared side at coordinates in the sorted list between the smallest and largest coordinates.
We have also invented a method of creating a conformal outline for layout of one or more devices on an integrated circuit that includes the steps of defining a plurality of input geometries in a coordinate system having a first axis and a second axis, where each input geometry has first and second edges parallel to the first axis and first and second sides parallel to the second axis. Coordinates on the first axis are acquired where the sides of each input geometry reside and a sorted list is formed of the acquired coordinates. A first candidate geometry is identified having its first side residing at the smallest coordinates in the sorted list and a second candidate geometry is identified having a second side residing at the largest coordinate in the sorted list. A third candidate geometry is also identified having its first and second sides residing between the smallest and largest coordinates in the sorted list. The second side of the first candidate geometry and the first side of the third candidate geometry are positioned at one coordinate in the sorted list between the smallest and largest coordinates in the sorted list thereby forming a first shared side. The second side of the third candidate geometry and the first side of the second candidate geometry are positioned at another coordinate in the sorted list between the one coordinate and the largest coordinate in the sorted list thereby forming a second shared side.
For each candidate geometry which has first axis coordinates which overlap first axis coordinates of one or more of the input geometries, and which has at least one second axis coordinate extreme which does not coincide with a second axis coordinate extreme of the one or more input geometries, the lengths of the sides of the candidate geometry are modified as necessary so that opposite ends of each side terminate at the respective second axis coordinate extremes of the one or more input geometries. When the shared side with respect to one candidate geometry does not coincide or completely overlap the shared side with respect to an adjacent candidate geometry, the length of the shared side with respect to the one candidate geometry is modified so that it coincides or completely overlaps the shared side with respect to the adjacent candidate geometry.
The method can also include determining a cost of the first, second and third candidate geometries and, if the thus determined cost is more advantageous than a previously determined cost or no cost, the thus determined cost is stored along with the positions of the first, second and third candidate geometries relative to the input geometries. The foregoing steps, after forming the second shared side, are repeated for each position of the second shared side at coordinates in the sorted list between the coordinate in the sorted list where the first shared side resides and the largest coordinate in the sorted list.
The method can further include repeating the foregoing steps, after forming the second shared side, for each position of the first shared side at coordinates in the sorted list between the one coordinate and the second from the largest coordinate in the sorted list.
Lastly, we have invented a method of creating a conformal outline for the layout of one or more devices on an integrated circuit. The method includes defining a plurality of adjoining candidate rectangles which encompass a plurality of input rectangles, where the outline of the adjoining rectangles define the conformal outline.
Preferably, each input rectangle has left and right sides, and top and bottom edges. Each candidate rectangle preferably has left and right sides, and top and bottom edges. Each pair of adjacent candidate rectangles define a shared side or edge that is coincident with the respective side or edge of at least one input rectangle.
The method can further include stepping each shared side or edge to at least one other side or edge, respectively, of one of the input rectangles and determining for each step of each shared side or edge a cost for the candidate rectangles. The outline of the candidate rectangles having the most advantageous cost is selected as the conformal outline.
The method can also include at least one of the following steps. First, for each step of each shared side, the lengths of the respective sides of at least the pair of candidate rectangles defining the shared side are adjusted whereupon the top and bottom edges of each pair of candidate rectangles are coincident with the topmost and bottommost edges of any input rectangles which overlap the candidate rectangle. Second, for each step of each shared edge, the lengths of the respective edges of at least the pair of candidate rectangles defining the shared edge are adjusted whereupon the left and right sides of each of the pair of candidate rectangles are coincident with the leftmost and rightmost sides of any input rectangles which overlap the candidate rectangle.